M-Group – Extending a Processor for Reliable Embedded Systems

Contact
Brent De Blaere – brent.deblaere@kuleuven.be
Jens Vankeirsbilck – jens.vankeirsbilck@kuleuven.be

Category
Electronics

Context

In recent years, extensible or customizable processors/ISAs have emerged, like RISC-V and Cadence Tensilica. With such customization, the implementation of software-implemented error detection techniques can be enhanced. The M-Group group is currently investigating ways to extend the RISC-V ISA with specialized instructions to support various error detection techniques.

The DistriNet research group of KU Leuven developed a highly extensible FPGA-friendly RISC-V processor model called VexRiscv that allows for easy experimentation with hardware extensions.

The goal of this project is to extend the VexRiscv processor with specialized instructions to support various error detection techniques. The implementation should be optimized to impose as little overhead as possible.

To verify the implementation, a test bench should be written to test if all instructions work as expected. Next, several programs utilizing the custom instructions should be tested on the synthesized FPGA to verify that they result in a correct output.

Objectives

• Research which instructions can be defined to aid with the detection of upsets
  
• Synthesize the VexRiscv processor model on an FPGA
  
• Extend the VexRiscv processor model with support for the custom instructions
  
• Verify the correctness of the implementation