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Webinar on Verilog HDL & Opportunities in VLSI Chip Design

May 7, 2020 @ 3:00 pm - 5:00 pm IST

Webinar on Verilog HDL & opportunities in VLSI Chip Design

Date : 7th May 2020

Time : 3 PM

Click here for registration

Organizer

IEEE Student Branch JNTUHCEH
Phone:
7013450011
Email:
jntuhcehieeestb@gmail.com