Summer School on Analog CMOS VLSI Circuit Design using Cadence

Summer School on Analog CMOS VLSI Circuit Design using Cadence

Date: 10 July 2019

The IEEE Students Branch of our college had organized a summer school on “Analog CMOS VLSI Circuit Design Using Cadence” during 17^th June to 29^th June 2019. The theory and practical sessions were conducted by Dr. K. B. Khanchandani and Prof. S. P. Badar. Total 17 students from second year E & TC participated and successfully completed the workshop. We are very much thankful to the college management, Hon’ Principal sir, Faculty Advisor Prof. P. R. Wankhede sir and the participants for the success of this workshop.