Reconfigurable digital hardware platforms such as field programmable gate arrays (FPGAs) can provide added advantages over real-time implementation of digital signal processing (DSP) algorithms via massive hardware level parallelism. Such hardware implementation of DSP algorithms typically requires mapping of a mathematical description of an algorithm to a suitable hardware implementation architecture, while taking into account speed, throughput and computational complexity constraints. This talk will discuss some of the commonly used design techniques to obtain hardware-friendly implementation architectures of simple DSP algorithms such as FIR/IIR filters. In particular, the talk will go through design concepts such as pipelining and parallel processing and provide some examples from FPGA implementation of simple DSP systems.

About the speaker

Dr. Chamith Wijenayake

School of Information Technology and Electrical Engineering, University of Queensland, Australia


Dr. Chamith Wijenayake completed his PhD in Electrical and Computer Engineering at the University of Akron, Ohio, USA in 2014 and BSc (Hons) degree in Electronic and Telecommunications Engineering with first class honours at the University of Moratuwa, Sri Lanka in 2007. His research interests and expertise include multidimensional signal processing algorithms and digital hardware architectures for antenna array based wideband beamforming and light field processing. His teaching interests and expertise span over the areas of embedded systems, FPGA based system design and signal processing. He is also exploring innovative practices in learning and teaching in the context of Engineering Education. He has received a number of awards including the Outstanding Student Research Award at the University of Akron, Ohio, USA, in 2011 and he is one of the two recipients of the IEEE Circuits and Systems Pre-Doctoral Award in 2014. From 2015-2019 he was a lecturer at the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, Australia.